Design of synchronous digital systems: timing diagrams, propagation delay, latches and flip- flops, shift registers and counters, Mealy/Moore finite state machines, Verilog, 2-phase clocking, timing analysis, CMOS implementation, S-RAM, RAM-based designs, ASM charts, state minimization.
5
UnitsLetter
Grading1, 2, 3
PasstimeUndergraduate students only
Level LimitEngineering
Collegekeep trying keep young.
Always learned smth from lectures. HW and midterm was fair. Labs are tough. But I am very dissapointed in how the final was graded. It was very rushed with them being unforgiven, making some of the questions all or nothing even though these questions were worth a lot. Not a good representation of overall knowledge.
Nobody finished early for the final. This man also stopped teaching and let the TA's teach in place of him. Even so, Peng literally read off the PowerPoint during lecture. Midterm was not bad, but the final exam was impossible to finish in 3 hours. I would rather wait and let prof Kim teach 152a.
Nice guy, but gave time consuming homework assignments and pretty hard tests. I did below average on the midterm and slightly above average on the final and ended up with a B. As long as you keep up with the content, you should be able to understand hw's, but they won't necessarily prepare you for the final, which had an average of below 50%.
Generally easy until the final. Midterm had similar enough problems to the study guide concepts, but the final was much harder, which was unexpected. Lectures were a little dull but decent enough. The 4 Labs weren't bad. 4 HWs, difficulty changed every week. 15% midterm, 30% final, 30% lab, 25% HW. For harder HW/labs he gave extensions. Nice guy!
Upamanyu Madhow
2.0
Joao Hespanha
4.9
Hua Lee
2.8
Yogananda Isukapalli
4.8