Hierarchical digital design both top-down and bottom-up with special emphasis on the role of wire loading, architecture design with partitioning, planning, and timing closure. Module and system interfaces and communication structural design. Design debugging using on chip JTAG based resources, static timing analysis, multiple clock domains, synchronization and computer peripheral design.
4
UnitsLetter
Grading1, 2, 3
PasstimeNone
Level LimitEngineering
College