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Hierarchical digital design both top-down and bottom-up with special emphasis on the role of wire loading, architecture design with partitioning, planning, and timing closure. Module and system interfaces and communication structural design. Design debugging using on chip JTAG based resources, static timing analysis, multiple clock domains, synchronization and computer peripheral design.

Prerequisites: ECE 152A with a minimum grade of C-; open to EE, CMPEN, and Computer Sciencmajors only.

4

Units

Letter

Grading

1, 2, 3

Passtime

None

Level Limit

Engineering

College
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